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PSMN3R5-30YL
N-channel TrenchMOS logic level FET
Rev. 01 -- 14 October 2008 Preliminary data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in industrial and communications applications.
1.2 Features and benefits
High efficiency due to low switching and conduction losses Suitable for logic level gate drive sources
1.3 Applications
Class-D amplifiers DC-to-DC converters Motor control Server power supplies
1.4 Quick reference data
Table 1. VDS ID Ptot Quick reference Conditions Tmb = 25 C; VGS = 10 V; see Figure 1; Tmb = 25 C; see Figure 2
[1]
Symbol Parameter drain current total power dissipation gate-drain charge
Min -
Typ -
Max 30 100 74
Unit V A W
drain-source voltage Tj 25 C; Tj 150 C
Dynamic characteristics QGD VGS = 4.5 V; ID = 10 A; VDS = 12 V; see Figure 14; see Figure 15 VGS = 10 V; ID = 15 A; Tj = 25 C; see Figure 12 5 nC
Static characteristics RDSon drain-source on-state resistance 2.2 3.5 m
[1]
Continuous current is limited by package.
NXP Semiconductors
PSMN3R5-30YL
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2. Pin 1 2 3 4 mb S S S G D Pinning information Symbol Description source source source gate mounting base; connected to drain
mbb076
Simplified outline
mb
Graphic symbol
D
G S
1234
SOT669 (LFPAK)
3. Ordering information
Table 3. Ordering information Type number Package Name Description PSMN3R5-30YL LFPAK plastic single-ended surface-mounted package (LFPAK); 4 leads
Version SOT669
4. Limiting values
Table 4. Symbol VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM EDS(AL)S Limiting values Parameter drain-source voltage drain-gate voltage gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature source current peak source current Tmb = 25 C; tp 10 s; pulsed; Tmb = 25 C
[1]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Conditions Tj 25 C; Tj 150 C Tj 25 C; Tj 150 C; RGS = 20 k VGS = 10 V; Tmb = 100 C; see Figure 1; VGS = 10 V; Tmb = 25 C; see Figure 1; tp 10 s; pulsed; Tmb = 25 C; see Figure 3 Tmb = 25 C; see Figure 2
[1] [1]
Min -20 -55 -55 -
Max 30 30 20 79 100 447 74 150 150 100 447 54
Unit V V V A A A W C C A A mJ
Source-drain diode
Avalanche ruggedness non-repetitive VGS = 10 V; Tj(init) = 25 C; ID = 100 A; Vsup 30 V; drain-source avalanche RGS = 50 ; unclamped energy
[1] Continuous current is limited by package.
PSMN3R5-30YL_1
(c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 14 October 2008
2 of 13
NXP Semiconductors
PSMN3R5-30YL
N-channel TrenchMOS logic level FET
120 ID (A) 100
003aac712
120 Pder (%) 80
03aa15
(1)
80
60
40
40
20
0 0 50 100 150 Tmb (C) 200
0 0 50 100 150 Tmb (C) 200
Fig 1.
Continuous drain current as a function of mounting base temperature
Fig 2.
Normalized total power dissipation as a function of mounting base temperature
003aac731
103 ID (A) 102 Limit RDSon = VDS / ID
10 s 100 s
10
DC 1 ms 10 ms
1
100 ms
10-1 10-1
1
10
VDS (V)
102
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN3R5-30YL_1
(c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 14 October 2008
3 of 13
NXP Semiconductors
PSMN3R5-30YL
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5. Symbol Rth(j-mb) Thermal characteristics Parameter Conditions Min Typ 0.6 Max 1.68 Unit K/W thermal resistance from see Figure 4 junction to mounting base
10 Zth(j-mb) (K/W) 1 = 0.5
003aac717
0.2 0.1
10-1
P = tp T
0.05 0.02
tp
t T
10
-2
single shot
10-6 10-5 10-4 10-3 10-2 10-1
tp (s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN3R5-30YL_1
(c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 14 October 2008
4 of 13
NXP Semiconductors
PSMN3R5-30YL
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6. Symbol V(BR)DSS VGS(th) Characteristics Parameter drain-source breakdown voltage gate-source threshold voltage Conditions ID = 250 A; VGS = 0 V; Tj = 25 C ID = 250 A; VGS = 0 V; Tj = -55 C ID = 1 mA; VDS = VGS; Tj = 25 C; see Figure 10; see Figure 11 ID = 1 mA; VDS = VGS; Tj = 150 C; see Figure 10 ID = 1 mA; VDS = VGS; Tj = -55 C; see Figure 10 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance VDS = 30 V; VGS = 0 V; Tj = 25 C VDS = 30 V; VGS = 0 V; Tj = 150 C VGS = 16 V; VDS = 0 V; Tj = 25 C VGS = -16 V; VDS = 0 V; Tj = 25 C VGS = 4.5 V; ID = 15 A; Tj = 25 C; see Figure 12 VGS = 10 V; ID = 15 A; Tj = 150 C; see Figure 13 VGS = 10 V; ID = 15 A; Tj = 25 C; see Figure 12 RG QG(tot) gate resistance total gate charge f = 1 MHz ID = 10 A; VDS = 12 V; VGS = 4.5 V; see Figure 14; see Figure 15 ID = 0 A; VDS = 0 V; VGS = 10 V ID = 10 A; VDS = 12 V; VGS = 10 V; see Figure 14; see Figure 15 QGS QGS(th) QGS(th-pl) QGD VGS(pl) Ciss Coss Crss td(on) tr td(off) tf
PSMN3R5-30YL_1
Min 30 27 1.3 0.65 -
Typ 1.7 3.18 2.2 0.53 19 37 41 6 4 2 5 2.4 2458 532 252 33 50 45 18
Max 2.15 2.45 1 100 100 100 5.6 6 3.5 -
Unit V V V V V A A nA nA m m m nC nC nC nC nC nC nC V pF pF pF ns ns ns ns
Static characteristics
Dynamic characteristics
gate-source charge pre-threshold gate-source charge post-threshold gate-source charge gate-drain charge gate-source plateau voltage input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time
ID = 10 A; VDS = 12 V; VGS = 4.5 V; see Figure 14; see Figure 15
VDS = 12 V; see Figure 14; see Figure 15 VDS = 12 V; VGS = 0 V; f = 1 MHz; Tj = 25 C; see Figure 16
-
VDS = 12 V; RL = 0.5 ; VGS = 4.5 V; RG(ext) = 4.7
-
(c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 14 October 2008
5 of 13
NXP Semiconductors
PSMN3R5-30YL
N-channel TrenchMOS logic level FET
Table 6. Symbol VSD trr Qr
Characteristics ...continued Parameter source-drain voltage reverse recovery time recovered charge Conditions IS = 25 A; VGS = 0 V; Tj = 25 C; see Figure 17 IS = 20 A; dIS/dt = -100 A/s; VGS = 0 V; VDS = 20 V Min Typ 0.88 [tbd] [tbd] Max 1.2 37 31 Unit V ns nC
Source-drain diode
80 ID (A) 60
003aac709
100 ID (A) 80
003aac710
10 VGS (V) = 4.5
3
2.8 60 40 40 Tj = 150 C 20 25 C 20 2.4 2.2 0 0 1 2 3 V (V) 4 GS 0 0 2 4 6 8 10 VDS (V) 2.6
Fig 5.
Transfer characteristics: drain current as a function of gate-source voltage; typical values
6
003aac711
Fig 6.
Output characteristics: drain current as a function of drain-source voltage; typical values
003aac716
4000 C (pF) Ciss
RDSon (m)
3000
Crss
4
2000
1000
2 2 4 6 8 VGS (V) 10
0 0 2 4 6 8 10 VGS (V)
Fig 7.
Drain-source on-state resistance as a function of gate-source voltage; typical values
Fig 8.
Input and reverse transfer capacitances as a function of gate-source voltage; typical values
PSMN3R5-30YL_1
(c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 14 October 2008
6 of 13
NXP Semiconductors
PSMN3R5-30YL
N-channel TrenchMOS logic level FET
120 gfs (S) 100
003aac718
3 VGS(th) (V) max 2 typ
003aab272
80
1.5 min 1
60
0.5
40 0 10 20 30 40 ID (A) 50
0 -60
0
60
120 Tj (C)
180
15
Fig 9. Forward transconductance as a function of drain current; typical values
003aab271
Fig 10. Gate-source threshold voltage as a function of junction temperature
6 RDSon (m) 5 VGS (V) = 3.2
003aac707
10-3 ID (A) 10-4 min typ
max
4 4.5
10-5
3 10
10-6 0 0.5 1 1.5 2 2.5 VGS (V)
2 0 20 40 60 80 I (A) 100 D
Fig 11. Sub-threshold drain current as a function of gate-source voltage
Fig 12. Drain-source on-state resistance as a function of drain current; typical values
PSMN3R5-30YL_1
(c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 14 October 2008
7 of 13
NXP Semiconductors
PSMN3R5-30YL
N-channel TrenchMOS logic level FET
2 a 1.6
003aab273
VDS ID VGS(pl)
1.2
VGS(th)
0.8
VGS QGS1 QGS2 QGD QG(tot)
003aaa508
0.4
QGS
0 -60
0
60
120
Tj (C)
180
Fig 14. Gate charge waveform definitions
Fig 13. Normalized drain-source on-state resistance factor as a function of junction temperature
10 VGS (V) 8 VDS = 12 (V) 6
1500
003aac715
3000 C (pF) 2500
003aac719
Ciss
VDS = 19 (V)
2000
Coss
4
1000
2
Crss 500
0 0 10 20 30 40 50 QG (nC)
0 10-1
1
10
VDS (V)
102
Fig 15. Gate-source voltage as a function of gate charge; typical values
Fig 16. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values
PSMN3R5-30YL_1
(c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 14 October 2008
8 of 13
NXP Semiconductors
PSMN3R5-30YL
N-channel TrenchMOS logic level FET
100 IS (A) 80
003aac708
60
40
Tj = 150 C
20
25 C
0 0.0
0.2
0.4
0.6
0.8
1.0 VSD (V)
Fig 17. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values
PSMN3R5-30YL_1
(c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 14 October 2008
9 of 13
NXP Semiconductors
PSMN3R5-30YL
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669
E b2 L1
A c2
A2
C E1 b3
mounting base D1 H D
b4
L2
1
e
2
3
b
1/2
4
wM A c X
e
A A1 C
(A 3)
detail X L yC 0 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A A1 A2 A3 b b2 b3 2.2 2.0 b4 0.9 0.7 c c2 D (1) D1(1) E(1) E1(1) max 5.0 4.8 3.3 3.1 e 1.27 H 6.2 5.8 L 0.85 0.40 L1 1.3 0.8 L2 1.3 0.8 w 0.25 y 0.1 8 0
1.20 0.15 1.10 0.50 4.41 0.25 1.01 0.00 0.95 0.35 3.62
0.25 0.30 4.10 4.20 0.19 0.24 3.80
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT669 REFERENCES IEC JEDEC MO-235 JEITA EUROPEAN PROJECTION ISSUE DATE 04-10-13 06-03-16
Fig 18. Package outline SOT669 (LFPAK)
PSMN3R5-30YL_1 (c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 14 October 2008
10 of 13
NXP Semiconductors
PSMN3R5-30YL
N-channel TrenchMOS logic level FET
8. Revision history
Table 7. Revision history Release date 20081014 Data sheet status Preliminary data sheet Change notice Supersedes Document ID PSMN3R5-30YL_1
PSMN3R5-30YL_1
(c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 14 October 2008
11 of 13
NXP Semiconductors
PSMN3R5-30YL
N-channel TrenchMOS logic level FET
9. Legal information
9.1 Data sheet status
Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Document status [1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
9.3
Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS -- is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PSMN3R5-30YL_1
(c) NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 -- 14 October 2008
12 of 13
NXP Semiconductors
PSMN3R5-30YL
N-channel TrenchMOS logic level FET
11. Contents
1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . .12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Contact information. . . . . . . . . . . . . . . . . . . . . .12
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: Rev. 01 -- 14 October 2008 Document identifier: PSMN3R5-30YL_1

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